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NB100LVEP222 Product Preview 2.5V/3.3V 1:15 Differential ECL/PECL /1//2 Clock Driver
The NB100LVEP222 is a low skew 1:15 differential /1//2 ECL fanout buffer designed with clock distribution in mind. The LVECL/LVPECL input signal pairs can be differential or used single-ended (with VBB output reference bypassed and connected to the unused input of a pair). Either of two fully differential clock inputs may be selected. Each of the four output banks of 2, 3, 4, and 6 differential pairs may be independently configured to fanout 1X or 1/2X of the input frequency. The LVEP222 specifically guarantees low output to output skew. Optimal design, layout, and processing minimize skew within a device and from lot to lot. This device is an improved version of the MC100LVE222 with higher speed capability and reduced skew. The fsel pins and CLK_Sel pin are asynchronous control inputs. Any changes may cause indeterminate output states requiring an MR pulse to resynchronize any 1/2X outputs (See Figure 3). Unused output pairs should be left unterminated (open) to reduce power and switching noise. The NB100LVEP222, as with most ECL devices, can be operated from a positive VCC supply in LVPECL mode. This allows the LVEP222 to be used for high performance clock distribution in +2.5/3.3 V systems. In a PECL environment series or Thevenin line, terminations are typically used as they require no additional power supplies. For more information on using PECL, designers should refer to Application Note AN1406/D. For a SPICE model, refer to Application Note AN1560/D. The VBB pin, an internally generated voltage supply, is available to this device only. For single-ended LVPECL input conditions, the unused differential input is connected to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs. When used, decouple VBB and VCC via a 0.01 mF capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VBB should be left open. Single-ended CLK input operation is limited to a VCC 3.0 V in LVPECL mode, ore VEE v 3.0 V in NECL mode.
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MARKING DIAGRAM*
NB100 LVEP222 AWLYYWW 52-LEAD LQFP THERMALLY ENHANCED CASE 848H FA SUFFIX A WL YY WW
52 1
= Assembly Location = Wafer Lot = Year = Work Week
*For additional information, see Application Note AND8002/D
ORDERING INFORMATION
Device NB100LVEP222FA Package LQFP-52 Shipping 160 Units/Tray
NB100LVEP222FAR2 LQFP-52 1500/Tape & Reel
* * * * *
20 ps Output-to-Output Skew 85 ps Part-to-Part Skew Selectable 1x or 1/2x Frequency Outputs LVPECL Mode Operating Range: VCC = 2.375 V to 3.8 V with VEE = 0 V NECL Mode Operating Range: VCC = 0 V with VEE = -2.375 V to -3.8 V Internal Input Pulldown Resistors
* * Performance Upgrade to ON Semiconductor's MC100LVE222 * VBB Output
This document contains information on a product under development. ON Semiconductor reserves the right to change or discontinue this product without notice.
(c) Semiconductor Components Industries, LLC, 2002
1
May, 2002- Rev. 2
Publication Order Number: NB100LVEP222/D
NB100LVEP222
VCC0
VCC0
VCC0 Qb2 Qb2 Qb1 Qb1 Qb0 Qb0 VCC0 Qa1 Qa1 Qa0 Qa0 VCC0
39 40 41 42 43 44 45 46 47 48 49 50 51 52 1
38
37
36
35
34
33
32
31
30
29
28
VCC0 27 26 25 24 23 22 21
Qc0
Qc0
Qc1
Qc1
Qc2
Qc2
Qc3
Qc3
NC
NC
Qd0 Qd0 Qd1 Qd1 Qd2 Qd2 Qd3 Qd3 Qd4 Qd4 Qd5 Qd5 VCC0
NB100LVEP222
20 19 18 17 16 15 14
2
3
4
5
6
7
8
9
10
11
12
13
CLK0
CLK0
MR
CLK1
CLK_Sel
CLK1
fsela
fselb
fselc
fseld L Active CLK0 /1
VBB
All VCC, VCCO, and VEE pins must be externally connected to appropriate Power Supply to guarantee proper operation. The thermally conductive exposed pad on package bottom (see package case drawing) must be attached to a heat-sinking conduit. This exposed pad is electrically connected to VEE internally.
VCC
Figure 1. 52-Lead LQFP Pinout (Top View) PIN DESCRIPTION
PIN CLK0*, CLK0** CLK1*, CLK1** CLK_Sel* MR* Qa0:1, Qa0:1 Qb0:2, Qb0:2 Qc0:3, Qc0:3 Qd0:5, Qd0:5 fseln* VBB VCC, VCCO VEE*** NC FUNCTION ECL Differential Input Clock ECL Differential Input Clock ECL Clock Select ECL Master Reset ECL Differential Outputs ECL Differential Outputs ECL Differential Outputs ECL Differential Outputs ECL 1 or 2 Select Reference Voltage Output Positive Supply Negative Supply No Connect Input MR CLK_Sel fseln
FUNCTION TABLE
Function H Reset CLK1 /2
* Pins will default LOW when left open. ** Pins will default HIGH when left open. *** The thermally conductive exposed pad on the bottom of the package is electrically connected to VEE internally.
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VEE
NB100LVEP222
MR CLK0 CLK0 /1 CLK1 CLK1 /2 2 Qa0:1 Qa0:1
CLK_SEL
VBB fsela 3 Qb0:2 Qb0:2 fselb 4 VCC VEE Qc0:3 Qc0:3 fselc 6 Qd0:5 Qd0:5 fseld
Figure 2. Logic Diagram
CLK
MASTER RESET
Q
1/2Q
Figure 3. Master Reset (MR) Timing Diagram
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NB100LVEP222
ATTRIBUTES
Characteristics Internal Input Pulldown Resistor Internal Input Pullup Resistor ESD Protection Human Body Model Machine Model Charged Device Model Value 75 kW 37.5 kW > 2 kV > 100 V > 2 kV Level 3 UL 94 V-0 @ 0.125 28 to 34 821 Devices
Moisture Sensitivity (Note 1) Flammability Rating Oxygen Index Transistor Count Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, refer to Application Note AND8003/D.
MAXIMUM RATINGS (Note 2)
Symbol VCC VEE VI Iout IBB TA Tstg JA JC Tsol Parameter PECL Mode Power Supply NECL Mode Power Supply PECL Mode In ut Voltage Input NECL Mode Input Voltage Output Current VBB Sink/Source Operating Temperature Range Storage Temperature Range Thermal Resistance (Junction-to-Ambient) (See Application Information) Thermal Resistance (Junction-to-Case) (See Application Information) Wave Solder 0 LFPM 500 LFPM 0 LFPM 500 LFPM < 2 to 3 sec @ 248C 52 LQFP 52 LQFP 52 LQFP 52 LQFP Condition 1 VEE = 0 V VCC = 0 V VEE = 0 V VCC = 0 V Continuous Surge VI VCC VI VEE Condition 2 Rating 6 -6 6 to 0 -6 to 0 50 100 0.5 -40 to +85 -65 to +150 35.6 30 3.2 6.4 265 Units V V V V mA mA mA C C C/W C/W C/W C/W C
2. Maximum Ratings are those values beyond which device damage may occur.
LVPECL DC CHARACTERISTICS VCC = 3.3 V; VEE = 0.0 V (Note 3)
-40C Symbol IEE VOH VOL VIH VIL VBB VIHCMR IIH IIL NOTE: 3. 4. 5. 6. Characteristic Power Supply Current Output HIGH Voltage (Note 4) Output LOW Voltage (Note 4) Input HIGH Voltage (Single-Ended) Input LOW Voltage (Single-Ended) Output Reference Voltage (Note 5) Input HIGH Voltage Common Mode Range (Differential) (Note 6) (Figure 5) Input HIGH Current Input LOW Current CLK CLK 0.5 -150 2155 1355 2135 1490 1775 1.2 1875 Min Typ 125 2280 1480 2405 1605 2420 1675 1975 3.3 150 0.5 -150 2155 1355 2135 1490 1775 1.2 1875 Max Min 25C Typ 125 2280 1480 2405 1605 2420 1675 1975 3.3 150 0.5 -150 2155 1355 2135 1490 1775 1.2 1875 Max Min 85C Typ 125 2280 1480 2405 1605 2420 1675 1975 3.3 150 Max Unit mA mV mV mV mV mV V mA mA
100LVEP circuits are designed to meet the DC specifications shown in the above table, after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintained. Input and output parameters vary 1:1 with VCC. VEE can vary + 0.925 V to -0.5 V. All loading with 50 W to VCC-2.0 V. Single ended input operation is limited VCC 3.0 V in LVPECL mode. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal.
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NB100LVEP222
LVPECL DC CHARACTERISTICS VCC = 2.5 V; VEE = 0 V (Note 7)
-40C Symbol IEE VOH VOL VIH VIL VIHCMR Characteristic Power Supply Current Output HIGH Voltage (Note 8) Output LOW Voltage (Note 8) Input HIGH Voltage (Single-Ended) (Note 9) Input LOW Voltage (Single-Ended) (Note 9) Input HIGH Voltage Common Mode Range (Differential) (Note 10) (Figure 5) Input HIGH Current Input LOW Current CLK CLK 0.5 -150 1355 555 1335 555 1.2 Min Typ 125 1480 680 1605 895 1620 875 2.5 1355 555 1335 555 1.2 Max Min 25C Typ 125 1480 680 1605 895 1620 875 2.5 1355 555 1275 555 1.2 Max Min 85C Typ 125 1480 680 1605 895 1620 875 2.5 Max Unit mA mV mV mV mV V
IIH IIL NOTE:
150 0.5 -150
150 0.5 -150
150
mA mA
100LVEP circuits are designed to meet the DC specifications shown in the above table, after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintained. 7. Input and output parameters vary 1:1 with VCC. VEE can vary + 0.125 V to -1.3 V. 8. All loading with 50 W to VCC - 2.0 V. 9. Do not use VBB at VCC < 3.0 V. 10. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal.
LVNECL DC CHARACTERISTICS VCC = 0.0 V; VEE = -3.8 V to -2.375 V (Note 11)
-40C Symbol IEE VOH VOL VIH VIL VBB VIHCMR Characteristic Power Supply Current Output HIGH Voltage (Note 12) Output LOW Voltage (Note 12) Input HIGH Voltage (Single Ended) Input LOW Voltage (Single Ended) Output Reference Voltage (Note 13) Input HIGH Voltage Common Mode Range (Differential) (Note 14) (Figure 5) Input HIGH Current Input LOW Current CLK CLK 0.5 -150 -1145 -1945 -1165 -1810 -1525 -1425 Min Typ 125 -1020 -1820 -895 -1695 -880 -1625 -1325 0.0 -1145 -1945 -1165 -1810 -1525 -1425 Max Min 25C Typ 125 -1020 -1820 -895 -1695 -880 -1625 -1325 0.0 -1145 -1945 -1165 -1810 -1525 -1425 Max Min 85C Typ 125 -1020 -1820 -895 -1695 -880 -1625 -1325 0.0 Max Unit mA mV mV mV mV mV V
VEE + 1.2
VEE + 1.2
VEE + 1.2
IIH IIL NOTE:
150 0.5 -150
150 0.5 -150
150
mA mA
100LVEP circuits are designed to meet the DC specifications shown in the above table, after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintained. 11. Input and output parameters vary 1:1 with VCC. 12. All loading with 50 W to VCC - 2.0 V. 13. Single ended input operation is limited VEE -3.0V in NECL mode. 14. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal.
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NB100LVEP222
AC CHARACTERISTICS VCC = 2.375 to 3.8 V; VEE = 0.0 V or VCC = 0.0 V; VEE = -2.375 to -3.8 V (Note 15)
-40C Symbol VOpp Characteristic Differential Output Voltage (Figure 4) fout < 100 MHz fout < 0.5 GHz fout < 1.0 GHz Propagation Delay (Differential) CLKx-QX MR-QX CLK_SEL-QX Within-Device Skew (Note 16) Device-to-Device Skew (Differential) (Note 17) Random Clock Jitter (Figure 4) (RMS) Input Swing (Differential) (Note 18) (Figure 5) Output Duty Cycle Output Rise/Fall Time 20%-80% 400 49.5 50 160 Min Typ 500 450 400 875 850 - 20 85 <1 1200 50.5 400 49.5 50 160 Max Min 25C Typ 600 550 450 875 850 - 20 85 <1 1200 50.5 49.5 50 160 Max Min 70C Typ 600 550 450 875 850 - 20 85 <1 1200 50.5 Max Unit mV mV mV ps ps ps ps ps ps
mV
tPLH tPHL
tskew
tJITTER VPP DCO tr/tf
% ps
15. Measured with LVPECL 750 mV source, 50% duty cycle clock source. All outputs loaded with 50 W to VCC - 2 V. 16. Skew is measured between outputs under identical transitions and operating conditions. 17. Device-to-Device skew for identical transitions at identical VCC levels. 18. VPP is the differential input voltage swing required to maintain AC characteristics including tPD and device-to-device skew. 800 700 600 VOPP (mV) 500 400 300 200 100 0 0 200 400 600 800 1000 1200 FREQUENCY (MHz) TBD 8 7 tJITTER ps (RMS) 6 5 4 3 2 1
Figure 4. Output Frequency (FOUT) versus Output Voltage (VOPP) and Random Clock Jitter (tJITTER)
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EE EE
NB100LVEP222
VCC(LVPECL) VIH(DIFF) VPP VIHCMR VIL(DIFF) VEE
Figure 5. LVPECL Differential Input Levels
Q Driver Device Q 50 W 50 W
D Receiver Device D
VTT VTT = VCC - 2.0 V
Figure 6. Typical Termination for Output Driver and Device Evaluation (Refer to Application Note AND8020 - Termination of ECL Logic Devices)
Resource Reference of Application Notes
AN1405 AND8002 AND8009
- - -
ECL Clock Distribution Techniques Marking and Date Codes ECLinPS Plus Spice I/O Model Kit
AND8020 - Termination of ECL Logic Devices For an updated list of Application Notes, please see our website at http://onsemi.com.
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NB100LVEP222
APPLICATIONS INFORMATION Using the thermally enhanced package of the NB100LVEP222 The NB100LVEP222 uses a thermally enhanced 52-lead LQFP package. The package is molded so that a portion of the leadframe is exposed at the surface of the package bottom side. This exposed metal pad will provide the low thermal impedance that supports the power consumption of the NB100LVEP222 high-speed bipolar integrated circuit and will ease the power management task for the system design. In multilayer board designs, a thermal land pattern on the printed circuit board and thermal vias are recommended to maximize both the removal of heat from the package and electrical performance of the NB100LVEP222. The size of the land pattern can be larger, smaller, or even take on a different shape than the exposed pad on the package. However, the solderable area should be at least the same size and shape as the exposed pad on the package. Direct soldering of the exposed pad to the thermal land will provide an efficient thermal conduit. The thermal vias will connect the exposed pad of the package to internal copper planes of the board. The number of vias, spacing, via diameters and land pattern design depend on the application and the amount of heat to be removed from the package. Maximum thermal and electrical performance is achieved when an array of vias is incorporated in the land pattern. The recommended thermal land design for NB100LVEP222 applications on multi-layer boards comprises a 4 X 4 thermal via array using a 1.2 mm pitch as shown in Figure 7 providing an efficient heat removal path.
All Units mm
supply enough solder paste to fill those vias and not starve the solder joints. The attachment process for the exposed pad package is equivalent to standard surface mount packages. Figure 8, "Recommended solder mask openings", shows a recommended solder mask opening with respect to a 4 X 4 thermal via array. Because a large solder mask opening may result in a poor rework release, the opening should be subdivided as shown in Figure 8. For the nominal package standoff of 0.1 mm, a stencil thickness of 5 to 8 mils should be considered.
All Units mm 0.2 1.0
1.0 4.6 0.2
4.6 Thermal Via Array (4 X 4) 1.2 mm Pitch 0.3 mm Diameter Exposed Pad Land Pattern
Figure 8. Recommended Solder Mask Openings
4.6
Proper thermal management is critical for reliable system operation. This is especially true for high-fanout and high output drive capability products. For thermal system analysis and junction temperature calculation the thermal resistance parameters of the package is provided:
Table 1. Thermal Resistance *
LFPM 0 100 qJA 5C/W 35.6 32.8 30.0 qJC 5C/W 3.2 4.9 6.4
4.6 Thermal Via Array (4 X 4) 1.2 mm Pitch 0.3 mm Diameter Exposed Pad Land Pattern
500
Figure 7. Recommended Thermal Land Pattern
The via diameter should be approximately 0.3 mm with 1 oz. copper via barrel plating. Solder wicking inside the via may result in voiding during the solder process and must be avoided. If the copper plating does not plug the vias, stencil print solder paste onto the printed circuit pad. This will
* Junction to ambient and Junction to board, four-conductor layer test board (2S2P) per JESD 51-8 These recommendations are to be used as a guideline, only. It is therefore recommended that users employ sufficient thermal modeling analysis to assist in applying the general recommendations to their particular application to assure adequate thermal performance. The exposed pad of the NB100LVEP222 package is electrically shorted to the substrate of the integrated circuit and VEE. The thermal land should be electrically connected to VEE.
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NB100LVEP222
PACKAGE DIMENSIONS
LQFP 52 LEAD EXPOSED PAD PACKAGE CASE 848H-01 ISSUE A
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MM. 3. DATUM PLANE E" IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING PLANE. 4. DATUM X", Y" AND Z" TO BE DETERMINED AT DATUM PLANE DATUM E". 5. DIMENSIONS M AND L TO BE DETERMINED AT SEATING PLANE DATUM T". 6. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.25 (0.010) PER SIDE. DIMENSIONS A AND B DO BASE METAL INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLAND E". 7. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED THE MAXIMUM D DIMENSION BY MORE THAN 0.08 (0.003). DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSION AND ADJACENT LEAD OR PROTRUSION 0.07 (0.003).
M M/2 -Z-
52 1
4 PL
AJ AJ
40 39
0.20 (0.008) T X-Y Z
PLATING
L
B
AB L/2
13 14 26 27
B/2
0.08 (0.003)
A/2 A DETAIL AH -E- -T-
SEATING PLANE
0.20 (0.008) E X-Y Z
AG
G
48 PL
AG
0.10 (0.004) T
D
52 PL M
0.08 (0.003)
T X-Y
Z
V 0.05 (0.002)
S
AD
EXPOSED PAD 13 14 26 27
S
C
K AE
W N F H DETAIL AH
1 52 40
39
VIEW AG-AG
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CCCC EEEE CCCC EEEE CCCC EEEE
D
REF M
-X-
-Y-
AA
J
Y T-U
Z
DIM A B C D F G H J K L M N P R S V W AA AB AC AD AE
DETAIL AJ-AJ
R AC
MILLIMETERS MIN MAX 10.00 BSC 10.00 BSC 1.30 1.50 0.22 0.40 0.45 0.75 0.65 BSC 1.00 REF 0.09 0.20 0.05 0.20 12.00 BSC 12.00 BSC 0.20 REF 0_ 7_ 0_ ----1.70 12 _ REF 12 _ REF 0.20 0.35 0.07 0.16 0.08 0.20 4.58 4.78 4.58 4.78
INCHES MIN MAX 0.394 BSC 0.394 BSC 0.051 0.059 0.009 0.016 0.018 0.030 0.026 BSC 0.039 BSC 0.004 0.008 0.002 0.008 0.472 BSC 0.472 BSC 0.008 REF 0_ 7_ 0_ ----0.067 12 _ REF 12 _ REF 0.008 0.014 0.003 0.006 0.003 0.008 0.180 0.188 0.180 0.188
P
0.25
GAGE PLANE
NB100LVEP222
Notes
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NB100LVEP222
Notes
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NB100LVEP222
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.
PUBLICATION ORDERING INFORMATION
Literature Fulfillment: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: ONlit@hibbertco.com N. American Technical Support: 800-282-9855 Toll Free USA/Canada JAPAN: ON Semiconductor, Japan Customer Focus Center 4-32-1 Nishi-Gotanda, Shinagawa-ku, Tokyo, Japan 141-0031 Phone: 81-3-5740-2700 Email: r14525@onsemi.com ON Semiconductor Website: http://onsemi.com For additional information, please contact your local Sales Representative.
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NB100LVEP222/D

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